Transistors and other semiconductor components are conventionally assembled in packages in which the various zones of each silicon body are soldered to respective external conductors. It is important that these assembled packages have low resistance contacts.
For many years, it was possible to make a solder contact at vias or contacts of a chip. This involved a process in which a physical mask (such as a molybdenum mask) was fit over a silicon wafer having numerous chips thereon, and held in place with tooling equipment. The contacts or vias were cleaned with a sputter etch process, and the entire assembly was then placed in a vacuum evaporator. Traditionally, a layer of chromium, followed by a layer of chrome-copper phased, followed by a layer of copper and then a layer of gold were deposited by evaporation. Other suitable techniques known to those skilled in the art, such as sputter deposition, could also be utilized. This metal composite has been referred to as a "ball limiting metallurgy" or "pad limiting metallurgy" (BLM or PLM, respectively).
Lead/tin solder was then evaporated upon the metal composite structure, to which the solder was capable of bonding. The mask was then removed and the entire assembly was subjected to temperature sufficient to melt the solder so that a hemispherical solder contact was formed over each via or contact. Depending upon the amount of solder used, the solder contact could be more than hemispherical as with a spherical shape truncated at the bottom.
The resulting chip with the numerous solder connections was then flipped, and the desired substrate was mated to the chip by again subjecting the structure to a temperature sufficient to melt the solder. This further temperature melting joins the solder contacts to the substrate.
This conventional technique for connecting a chip and a substrate via a solder contact had numerous advantages over the previously used methods. One advantage is that the numerous connections were made at one time, which is beneficial for mass production. Another advantage was that melting of the solder operated to self-align the chip and the substrate due to the surface tension of the melting solder. A further advantage was that, unlike a wire bond chip which is limited to a perimeter set of pad connections because a wire must be connected to each, this technique allowed formation of arrays of contacts all over the chip.
Despite these advantages of the chrome copper gold connection method, further developments in the semiconductor technology have revealed disadvantages. For instance, as the semiconductor industry has advanced, the size of silicon wafers has increased from five inches to eight inches. Furthermore, the number of connections desired per chip has increased from around 100-400 to over 1500 per chip. Also, the diameter of the PLM material has decreased from around 150 microns to 100 or less microns. Taking all of these developments into consideration, smaller PLM was desired, with many more PLM connections per chip, and the chips were mounted on larger silicon wafers.
Problems are associated with these developments. For example, the necessary molybdenum mask alignment can be affected by the temperatures required to evaporate the metal composite for connecting the solder contact, due to expansion differences of the various metals used. Furthermore, the technology of making a molybdenum mask limits the diameter of any hole in the mask to the thickness of the mask. Therefore, if a hole of only 100 microns is required in the mask, the molybdenum itself can only be 100 microns thick. This results in a very flexible mask and again causes alignment problems. For financial purposes, it is also desirable to reuse a mask. In order to reuse a mask, it must be removed as an entire structure and cleaned. A very thin, flexible molybdenum mask is likely to be damaged when such attempts at reuse are made.
It is possible to use a photo resist liftoff mask. However, such a photo resist liftoff mask is not compatible with the conventional chrome-copper-gold (Cr--Cu--Au) metallization because the metallization is deposited at room temperature. In order to have reasonable stress levels, the Cr--Cu--Au metallization is, for example, generally deposited above about 150.degree. C. As stated above, this is incompatible with most photo resist liftoff mask procedures.
Additionally, in the production of some semiconductor devices, multiple chip join cycles and rework are required. This leads to a problem of failure at one or more interfaces of multi-layer metal structures used in the device. Furthermore, failure can be accelerated by exposure to required process chemicals, such as perchlorethylene and chlorine/flux mixtures, or exposure during required heating cycles. The degree of damage is cumulative with multiple flux applications, reflows (365.degree. C.), and flux clean cycles, even with xylene solvents.
A need thus exists for a way to connect chips on a silicon wafer to a substrate using solder contacts, in which the problems of earlier connection methods are overcome. The new method should also overcome the problems of interface failure encountered with multilayer metal composites.